The present invention relates to an output unit for a charge transfer device (hereinafter referred to as a "CTD") and, more particularly, to a reference voltage generator for a voltage step-up circuit for applying a stepped-up voltage to a drain.
CTDs are widely used in solid state image sensors, charge transfer type delay lines, comb line filters, transversal filters, and so forth. A floating diffusion system is a known type of semiconductor integrated CTD signal output system. One of a number of CTDs which employ a floating diffusion system with step-up circuit is disclosed in FIGS. 4 and 5 of Japanese Patent Disclosure No. Sho 59-132668, invented by the inventor of the present invention, Mr. Imai. The construction and the operation of the CTD with the step-up circuit will be described with reference to FIGS. 1 and 2.
An analog signal is input through terminal 1 to input unit 7 of CTD shown in FIGS. 1 and 2. Input unit converts the input signal to a signal charge with a charge amount corresponding to the level of the input signal, and also adds to this signal charge a predetermined DC bias charge. The resulting signal charge is then transferred toward floating diffusion region 9 by charge transfer unit 8. Charge transfer unit 8 comprises a front surface region of semiconductor substrate 5 and transfer electrodes 17i, 18i (i is l to n). Transfer electrodes 17i, 18i transfer the signal charges of semiconductor substrate 5 according to two clock pulses .phi.1, .phi.2. The transferred signal charges are fed under output gate electrode 1 to floating diffusion region 9. Reset voltage VGG, higher than power source voltage VDD, is applied by step-up circuit 19 to drain region 11. When reset pulse .phi.R applied to reset gate electrode 13 is low voltage VRL, potential value PRL under reset gate electrode 13 becomes a value for electrically interrupting drain region 1 and floating diffusion region 9 as shown in FIG. 3A. When reset pulse .phi.R becomes high voltage VRH, potential value PRH under reset gate electrode 13 becomes a value for conducting floating diffusion region 9 and drain region 11. The charge of floating diffusion region 9 is discharged (absorbed) under reset gate electrode 13 to drain region 11, and floating diffusion region 9 is reset to voltage VGG. When reset pulse .phi.R again becomes low voltage VRL, floating diffusion region 9 becomes a floating state to wait for the next charge input.
FET 14 of output circuit 16 is connected at its gate to floating diffusion region 9, and a constant current flows from current source 15 to a current path. FET 14 converts the signal charge fed to floating diffusion region 9 to voltage signal, and outputs voltage signal VOUT. The dynamic range of output signal VOUT is proportional to the difference (PD-PG)=DR between potential PD and potential PG under output gate electrode 10. Therefore, when applied voltage VB of output gate electrode 10 is set to the allowable value as low as possible with respect to potential PnL under transfer electrode 18n of the final stage, the dynamic range of the output signal of the CTD in FIGS. 1 and 2 becomes considerably larger than that of the output signal of the CTD applied with power source voltage VDD to drain region 11 since voltage VGG is higher than power source voltage VDD. The CTD can increase the charge containing capacity of floating diffusion region 9 without increasing the capacity of floating diffusion region 9.
When floating diffusion region 9 is reset, voltage VGG is also applied to the gate of FET 14. When the gate voltage of FET 14 at signal detecting time is denoted by VG, the voltage between the drain and the source is VDS, the voltage between the gate and the source is VGS, the threshold voltage of MOS transistor 14 is VTHE and the source voltage (the voltage of output terminal 2) is VO, the following equations (1) and (2) are satisfied. EQU VDS=VDD-VO (1) EQU VGS-VTHE=VG-VO-VTHE (2)
It is necessary to satisfy the following formula to saturate FET 14 at signal detection time. EQU VGS-VTHE&lt;VDS (3)
When the equations (1) and (2) are substituted for the formula (3), the following formula (4) is satisfied. EQU VG-VTHE&lt;VDD (4)
Therefore, when an output voltage having good linearity is required, it is necessary to determine the voltage relation so as to satisfy the above formula (4) at the signal detection time.
Then, step-up circuit 19 for applying voltage VGG higher than power source voltage VDD to drain region 11 will be described. FIG. 4 shows a step-up circuit disclosed in FIG. 7 of the Japanese Patent Disclosure. Step-up circuit 19 in FIG. 4 has reference voltage generator 20 including depletion type MOS transistors 21, 22; and step-up portion 30 including MOS transistor 31, MOS transistor 32 and capacitor 33. MOS transistors 21, 22 have the same conductivity type as that of MOS transistor (MOS transistor including regions 9, 11 and electrode 13) for forming reset means 12 of the CTD.
In FIG. 4, when clock pulse CP is a low level and clock pulse CP is a high level, MOS transistor 31 is turned on, MOS transistor 32 is turned off, capacitor 33 is charged, and the voltage across capacitor 33 becomes VREF (the output voltage of node 23). When clock pulse CP then becomes high level, MOS transistor 31 is turned off, second MOS transistor 32 is turned on, and the output voltage of node 34 is raised by "the peak value of clock pulse CP minus threshold value VTH of MOS transistor 32" higher than voltage VREF.
However, when reference voltage generator 20 in FIG. 4 is used as a reference voltage generator of drain step-up circuit 19 of the CTD, the following drawbacks occur. The higher output voltage VGG rises in the CT in FIGS. 1 and 2, the wider dynamic range DR shown in FIG. 3B becomes. When the potential of drain region 11 becomes higher than potential PRH under reset gate electrode 13 as a pulse of High level is applied to reset gate electrode 13, it is necessary to raise reset pulse .phi.R. When bias voltage VFD of the signal at floating diffusion region 9 is set to as high as VDD+VTHE, transistor 14 of signal processor (output circuit) 16 enters nonsaturated state to lose the linearity of the output signal. Therefore, the upper limit of the step-up level coincides with the maximum value for maintaining the linearity indicated by formula (4). When formula (4) is transformed, the following formula (4') is obtained EQU VG&lt;VDD+VTHE (4')
Since VG=VFD exists, the following formula (4") is satisfied EQU VFD&lt;VDD+VTHE (4")
When the capacity of floating diffusion region 9 is indicated by CFD and charge transferred to the floating diffusion region is indicated by Qs, the following equation (5) is satisfied. EQU VFD=VGG-(Qs/CFD) (5)
Qs/CFD corresponds to the voltage component of the signal charge of floating diffusion region 9. Therefore, the following equation (6) is satisfied. EQU VGG-(Qs/CFD)=VFD&lt;VDD+VTHE (6)
The lower limit of voltage VGG must be larger than potential value PnL under the transfer electrode 18n. Therefore, the following equation (7) is satisfied. EQU .vertline.VTHD.vertline.&lt;VGG-(Qs/CFD)=VFD&lt;VDD+VTHE (7)
The VTHD is the threshold value of the D-type MOS transistor formed of regions 9, 11 and electrode 13, and VTHD=PnL=approx. PG.
Threshold value VTHD of the depletion transistor and threshold value VTHE of the enhancement transistor are independently varied by process variations, e.g., the thickness of insulating film 6 in FIG. 2, the irregularity of ion density of ions to be implanted, the depth of the layer of implanted ions, and the irregular gate of the impurity density of the semiconductor substrate. However, since reference voltage generator 20 in FIG. 4 is composed of the same conductivity type MOS transistors, output voltage VGG is constant irrespective of the process variations. Thus, when .vertline.VTHD.vertline. is, for example, large, the tolerance of the lower limit of VFD is small from equation (7), and when VTHE is small, the tolerance of the upper limit of the VFD is small from equation (7).
In FIG. 3B, voltage VGG (which does not alter by the process variation) is applied to the drain region, potential PD is constant. When insulating film 6 is, for example, thickened, potential PG (=approx. PnL) is deepened, and dynamic range DR is reduced. Thus, the conventional art has such a disadvantage that CTD characteristic is altered due to the process variation.